EDA

Scalable Simulation Architectures: Designs and deploys full-stack simulation environments that unify Instruction Accurate (IA), Cycle Accurate (CA), and RTL workflows.

EDA Tooling & Integration: Develops robust infrastructure to support the complete IP lifecycle. Orchestrates massive parallelization of SystemC models using Kubernetes clusters, enabling high-throughput regression testing and validation. Bridges the gap between abstract modeling and silicon verification by integrating industry-standard EDA tools into cohesive, automated pipelines.

Advanced Compiler Engineering: Manages and optimizes complex build toolchains based on Clang and LLVM to support novel hardware architectures.

CHERI & Security Integration: Implements and maintains compiler backends for CHERI (Capability Hardware Enhanced RISC Instructions), ensuring robust memory safety and fine-grained security at the ISA level. Specializes in adapting toolchains for custom hardware extensions, optimizing code generation for specific micro-architectures, and streamlining cross-compilation environments for embedded targets.

Automated Architecture Analysis: Drives data-driven decision-making through automated Design Space Exploration (DSE) frameworks.

Multi-Objective Optimization: Evaluates architectural trade-offs by systematically analyzing Power, Performance, and Area (PPA) metrics against varying workloads. Utilizes parametric scripts and simulation feedback loops to identify optimal hardware configurations, significantly reducing design iteration time and ensuring target specifications are met prior to RTL freeze.